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MX25L1605DZNI-12G 参数 Datasheet PDF下载

MX25L1605DZNI-12G图片预览
型号: MX25L1605DZNI-12G
PDF下载: 下载PDF文件 查看货源
内容描述: 16M - BIT [X 1 / X 2 ] CMOS串行闪存 [16M-BIT [x 1 / x 2] CMOS SERIAL FLASH]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 56 页 / 994 K
品牌: MCNIX [ MACRONIX INTERNATIONAL ]
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MX25L1605D
MX25L3205D
MX25L6405D
Status Register Feature
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID
HARDWARE FEATURES
SCLK Input
-
Serial clock input
• SI Input
-
Serial Data Input
• SO Output
-
Serial Data Output
• WP#/ACC pin
-
Hardware write protection and program/erase acceleration
• HOLD# pin
-
pause the chip without diselecting the chip
• PACKAGE
-
16-pin SOP (300mil)
- 8-land WSON (8x6mm or 6x5mm)
-
8-pin SOP (200mil, 150mil)
-
8-pin PDIP (300mil)
- 8-land USON (4x4mm)
-
All Pb-free devices are RoHS Compliant
ALTERNATIVE
• Security Serial Flash (MX25L1615D/MX25L3215D/MX25L6415D) may provides additional protection features for op-
tion. The datasheet is provided under NDA.
GENERAL DESCRIPTION
The MX25L1605D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in
two I/O read mode, the structure becomes 8,388,608 bits x 2. The MX25L3205D are 33,554,432 bit serial Flash memory,
which is configured as 4,194,304 x 8 internally. When it is in two I/O read mode, the structure becomes 16,772,216 bits
x 2. The MX25L6405D are 67,108,864 bit serial Flash memory, which is configured as 8,388,608 x 8 internally. When it
is in two I/O read mode, the structure becomes 33,554,432 bits x 2. (please refer to the "Two I/O Read mode" section).
The MX25L1605D/3205D/6405D feature a serial peripheral interface and software protocol allowing operation on a simple
3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output.
The MX25L1605D/3205D/6405D provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified
page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis,
or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), or block (64K-byte),
or whole chip basis.
P/N: PM1290
REV. 1.4, OCT. 01, 2008
2