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MX29F080TC-90 参数 Datasheet PDF下载

MX29F080TC-90图片预览
型号: MX29F080TC-90
PDF下载: 下载PDF文件 查看货源
内容描述: 8M - BIT [ 1024K ×8 ] CMOS EQUAL部门FLASH MEMORY [8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 38 页 / 607 K
品牌: Macronix [ MACRONIX INTERNATIONAL ]
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MX29F080  
CAPACITANCE (TA = 25oC, f = 1.0 MHz)  
SYMBOL  
CIN1  
PARAMETER  
MIN.  
TYP  
MAX.  
8
UNIT  
pF  
CONDITIONS  
VIN = 0V  
Input Capacitance  
Control Pin Capacitance  
Output Capacitance  
CIN2  
12  
pF  
VIN = 0V  
COUT  
12  
pF  
VOUT = 0V  
READ OPERATION  
DC CHARACTERISTICS (TA = 0°CTO 70°C,VCC = 5V±10%)  
SYMBOL PARAMETER  
MIN.  
TYP  
MAX.  
±1  
±1  
1
UNIT  
uA  
uA  
mA  
uA  
mA  
mA  
V
CONDITIONS  
ILI  
Input Leakage Current  
VIN = GND to VCC  
VOUT = GND to VCC  
CE = VIH  
ILO  
Output Leakage Current  
Standby VCC current  
ISB1  
ISB2  
ICC1  
ICC2  
VIL  
0.2  
5
CE = VCC + 0.3V  
IOUT = 0mA, f=1MHz  
IOUT = 0mA, f=10MHz  
Operating VCC current  
30  
50  
0.8  
Input Low Voltage  
-0.3(NOTE 1)  
2.0  
VIH  
Input High Voltage  
VCC + 0.3  
0.45  
V
VOL  
VOH1  
VOH2  
Output Low Voltage  
Output High Voltage(TTL)  
V
IOL = 2.1mA  
IOH = -2mA  
2.4  
V
Output High Voltage(CMOS) VCC-0.4  
V
IOH = -100uA,  
VCC=VCC MIN  
NOTES:  
1. VIL min. = -1.0V for pulse width < 50 ns.  
VIL min. = -2.0V for pulse width < 20 ns.  
2. VIH max. = VCC + 1.5V for pulse width < 20 ns.  
If VIH is over the specified maximum value, read operation  
cannot be guaranteed.  
AC CHARACTERISTICS (TA = 0oC to 70oC,VCC = 5V±10%)  
29F080-70*  
29F080-90  
29F080-12  
SYMBOL PARAMETER  
MIN. MAX. MIN. MAX. MIN. MAX.  
UNIT  
ns  
CONDITIONS  
CE=OE=VIL  
OE=VIL  
tACC  
tCE  
tOE  
tDF  
Address to Output Delay  
70  
70  
40  
20  
90  
90  
40  
30  
120  
120  
50  
CE to Output Delay  
ns  
OE to Output Delay  
ns  
CE=VIL  
OE High to Output Float (Note1)  
Address to Output hold  
0
0
0
0
0
0
30  
ns  
CE=VIL  
tOH  
ns  
CE=OE=VIL  
TEST CONDITIONS:  
NOTE:  
Input pulse levels: 0.45V/2.4V*  
Input rise and fall times is equal to or less than 0ns  
1. tDF is defined as the time at which the output achieves the  
open circuit condition and data is no longer driven.  
* For -70, the input levels : 0.0/3.0V, the output load : 1TTL  
gate+30pF (including scope and jig)  
Output load: 1 TTL gate + 100pF* (Including scope and jig)  
Reference levels for measuring timing: 0.8V, 2.0V  
P/N:PM0579  
REV. 1.4, JAN. 16, 2002  
14