MX29L1611
DATA PROTECTION
The MX29L1611 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read Array
mode. Also,withitscontrolregisterarchitecture,alteration
of the memory contents only occurs after successful
completion of specific multi-bus cycle command
sequences.
Thedevicealsoincorporatesseveralfeaturestoprevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up
andpower-down,awritecycleislockedoutforVCCless
thanVLKO(typically1.8V). IfVCC<VLKO,thecommand
registerisdisabledandallinternalprogram/erasecircuits
are disabled. Under this condition the device will reset
tothereadmode. Subsequentwriteswillbeignoreduntil
the VCC level is greater than VLKO. It is the user's
responsibilitytoensurethatthecontrolpinsarelogically
correct to prevent unintentional write when VCC is
above VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noisepulsesoflessthan10ns(typical)on CEorWEwill
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM0511
REV. 2.4, NOV. 06, 2001
14
Macronix [ MACRONIX INTERNATIONAL ]
