MX93002
FUNCTIONAL DESCRIPTION
. Clock Rate (REG4 bit(2))
. The clock rate (MCLK) must be set before user uses the function of the MX93002;
. Programmable clock rate :
1. 2.048MHz (Frame Sync. 8KHz);
2. 1.536MHz (Frame Sync. 8KHz);
. Data Format (REG4 bit(1,0))
. The data format must be set before user uses the function of the MX93002;
. Programmable Data Format
1. 16-bit linear data format. It can have 14-bit resolution and higher linearity than u/a-law format has;
2. 8-bit u-law data format;
3. 8-bit a-law data format;
. PCM CODEC
. The block includes
A/D
&
D/A
converters and all digital filters;
1.
A/D
&
D/A
Converters
A/D
Channel :
A. Input Range : 0 ~ 3Vpp (3Vpp as A/D 0dB full swing (0dB
FS
));
B. Digital Filters : For the purpose of out-of-band noise filtering, IIR digital filters are implemented on the
same chip ( >26dB / 60Hz; <1dB / 300Hz ~ 3.4KHz; >14dB / 3.6KHz ~ 4.6KHz; >32dB / >4.6KHz );
D/A
Channel :
A. Output swing : 0 ~ 3Vpp (3Vpp as D/A 0dB full swing (0dB
FS
));
B. Digital Filters :
a. G.711 specification;
b. The digital input applied to D/A converter can not be a DC signal other than idle (bits all zero), as
limit cycles in the embodiment method at a level of -70dBm will present at the analog output.
. Power Down Mode
. The MX93002 will recover from power-down mode when MCLK keeps a consistent clock (1.536 or 2.048MHz);
. Support system power (Adapter and Battery) detection. The function will work well even under 3V power supply;
. Support automatic power-down control when
MCLK
keeps high or low;
. Support 4 power-down modes for special applications:
MODE
FUNCTION
VBG
reference
POW
&
BAT
all analog blocks
A/D and D/A
REG 6 (7,6)
REG 6 (7,6)
REG 6 (7,6)
REG 6 (7,6)
(SLEEPA,SLEEP) = ( 0,0 ) (SLEEPA,SLEEP) = ( 0,1 ) (SLEEPA,SLEEP) = ( 1,0 ) (SLEEPA,SLEEP) = ( 1,1 )
on
on
off
off
off
off
off
off
Table 1
off
on
off
off
on
on
on
off
7
MCNIX [ MACRONIX INTERNATIONAL ]
