1Gb: x4, x8, x16 DDR3 SDRAM
Operations
Figure 93:
CK#
CK
T0
WRITE (BL8) to PRECHARGE
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Address
Valid
WL = AL +
CWL
tWR
Valid
DQS, DQS#
DQ BL8
DI
n
DI
n
+1
DI
n
+2
DI
n
+3
DI
n
+4
DI
n
+5
DI
n
+
6
DI
n
+7
Indicates A Break in
Time
Scale
Transitioning Data
Don’t
Care
Notes:
1. DI
n
= data-in from column
n.
2. Seven subsequent elements of data-in are applied in the programmed order following
DO
n.
3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 94: WRITE (BC4 Mode Register Setting) to PRECHARGE
CK#
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Address
Valid
WL = AL +
CWL
tWR
Valid
DQS, DQS#
DQ BC4
DI
n
DI
n
+1
DI
n
+2
DI
n
+3
Indicates A Break in
Time
Scale
Transitioning Data
Don’t
Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. The write recovery time (
t
WR) is referenced from the first rising clock edge after the last
write data is shown at T7.
t
WR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI
n
= data-in for column
n.
5. BC4 (fixed), WL = 5, RL = 5.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
146
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