1Gb: x4, x8, x16 DDR3 SDRAM
Operations
Figure 96: Data Input Timing
DQS, DQS#
tWPRE
DQ
DM
tDS
tDQSH
DI
b
tDQSL
tWPST
tDH
Transitioning Data
Don’t
Care
PRECHARGE
Input A10 determines whether one bank or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
SELF REFRESH
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
The DRAM must be idle with all banks in the precharge state (
t
RP is satisfied and no
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see “On-Die Termination (ODT)” on page 160 for timing
requirements). If R
TT
_
NOM
and R
TT
_
WR
are disabled in the mode registers, ODT can be a
“Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW
to keep the DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, become “Don’t Care.” The DRAM initiates a minimum of one REFRESH
command internally within the
t
CKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
t
CK
specifications) when self refresh mode is entered. If the clock remains stable and the
frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self
refresh mode after
t
CKESR is satisfied (CKE is allowed to transition HIGH
t
CKESR later
than when CKE was registered LOW). Since the clock remains stable in self refresh mode
(no frequency change),
t
CKSRE and
t
CKSRX are not required. However, if the clock is
altered during self refresh mode (turned-off or frequency change), then
t
CKSRE and
t
CKSRX must be satisfied. When entering self refresh mode,
t
CKSRE must be satisfied
prior to altering the clock's frequency. Prior to exiting self refresh mode,
t
CKSRX must be
satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for
t
XS time.
t
XS
is required for the completion of any internal refresh that is already in progress and must
be satisfied before a valid command not requiring a locked DLL can be issued to the
device.
t
XS is also the earliest time self refresh reentry may occur (see Figure 97 on
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1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
148
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MDTIC [ Micon Design Technology Corporation ]
