MDT10P157
8. Reset Condition for all Registers
Register
CPIO A
CPIO B
CPIO C
TMR
Address
－－
Power-On Reset
1111 1111
1111 1111
1111 1111
1111 1111
－
/MCLR or WDT Reset
1111 1111
1111 1111
1111 1111
1111 1111
－
－－
－－
－－
IAR
00h
01h
02h
03h
04h
05h
06h
07h
RTCC
PC
xxxx xxxx
1111 1111
0001 1xxx
100x xxxx
- - - - xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
1111 1111
000# #uuu
100u uuuu
- - - - uuuu
uuuu uuuu
uuuu uuuu
STATUS
MSR
PORT A
PORT B
PORT C
Note : u = unchanged, x = unknown, - = unimplemented, read as “0”
# = value depends on the condition of the following table
Condition
Status: bit 4 Status: bit 3
/MCLR reset (not during SLEEP)
/MCLR reset during SLEEP
WDT reset (not during SLEEP)
WDT reset during SLEEP
u
1
0
0
u
0
1
0
This specification are subject to be changed without notice. Any latest information please visit
httpl;e//awswe wp.rmevditeicw.cohmttp.t;w//www.mxmcu.com.cn P.8
2010/06 VER 1.0
MDTIC [ Micon Design Technology Corporation ]
