MDT10P65
10.
Instruction Set
Instruction Code
Mnemonic
Operands
Function
No operation
Clear Watchdog timer
Sleep mode
Load W to TMODE register
Control I/O port register
Store W to register
Load register
Operation
None
0→WT
0→WT,
stop OSC
W→TMODE
W→CPIO
W→R
R→t
I→W
[R(0~3)
↔
R(4~7)]→t
R + 1→t
R + 1→t
W + R→t
r
TF, PF
TF, PF
None
None
None
Z
None
None
Z
None
C, HC, Z
Status
010000 00000000
NOP
010000 00000001
CLRWT
010000 00000010
SLEEP
010000 00000011
TMODE
010000 00000rrr
CPIO R
010001 1rrrrrrr
STWR R
011000 trrrrrrr
LDR R, t
111010 iiiiiiii
LDWI I
Load immediate to W
010111 trrrrrrr
SWAPR R, t Swap halves register
011001 trrrrrrr
INCR R, t Increment register
011010 trrrrrrr
INCRSZ R, t Increment register, skip if
zero
011011 trrrrrrr
ADDWR R, t Add W and register
011100 trrrrrrr
SUBWR R, t Subtract W from register
011101 trrrrrrr
DECR R, t
011110 trrrrrrr
DECRSZ R,
t
010010 trrrrrrr
ANDWR R, t
110100 iiiiiiii
ANDWI i
Decrement register
Decrement register, skip if
zero
AND W and register
AND W and immediate
C, HC, Z
R
﹣W→t
(R+/W+1→t)
R
﹣1→t
R
﹣1→t
R
∩
W→t
i
∩
W→W
R
∪
W→t
i
∪
W→W
R
♁
W→t
Z
None
Z
Z
Z
Z
Z
Z
Z
C
010011 trrrrrrr
IORWR R, t Inclu. OR W and register
110101 iiiiiiii
IORWI i
Inclu. OR W and immediate
010100 trrrrrrr
XORWR R, t Exclu. OR W and register
110110 iiiiiiii
XORWI i Exclu. OR W and immediate i
♁
W→W
011111 trrrrrrr
COMR R, t Complement register
/R→t
010110 trrrrrrr
RRR R, t Rotate right register
R(n)
→
R(n-1), C→
R(7),
R(0)→C
010101 trrrrrrr
RLR R, t Rotate left register
R(n)→r(n+1),
C→R(0),
R(7)→C
010000 1xxxxxxx
CLRW
Clear working register
0→W
C
Z
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 11
2005/10
Ver. 1.6
MDTIC [ Micon Design Technology Corporation ]
