MDT14F201
(19) DBCTL: R13
PB0 input de-bounce control register
Bit
0
4~1
Symbol
DBEN
DEBNL3
~
DEBNL0
7~5
DEBNH2
~
DEBNH0
(20) CCP1L: R15
Capture/Compare/PWM LSB
(21) CCP1H: R16
Capture/Compare/PWM MSB
0: Disable PB0 input de-bounce
1: Enable PB0 input de-bounce
Low pulse de-bounce control
If Fosc=16MHz,
detect pulse 0000:0uS, 0001:1uS, 0010:2uS, ~ ,1111:15uS
How pulse de-bounce control
If Fosc=16MHz,
detect pulse 000:0uS, 001:1uS, 010:2uS, ~ ,111:7uS
Function
(22) CCP1CTL: R17
Bit
3~0
Symbol
CCP1M3
~
CCP1M0
0 0 0 0: CCP1 off
0 1 0 0: Capture1 mode, every falling edge
0 1 0 1: Capture1 mode, every rising edge
0 1 1 0: Capture1 mode, every 4
th
rising edge
0 1 1 1: Capture1 mode, every 16
th
rising edge
1 0 0 0: Compare1 mode, set output on match
1 0 0 1: Compare1 mode, clear output on match
1 0 1 0: Compare1 mode, generate software interrupt on match
1 0 1 1: Compare1 mode, trigger special event
1 1 x x: PWM1 mode
5~4
7~6
PWM1LSB These bits are the two LSBs of the PWM1 duty cycle
--
Unimplemented
Function
Preliminary
P.10
2010/8 Ver. 0.3
MDTIC [ Micon Design Technology Corporation ]
