MDT14F201
(36) PCPHR: R95
PCPHR
Bit 7
PHC7
Bit 6
PHC6
Bit 5
PHC5
Bit 4
PHC4
Bit 3
PHC3
Bit 2
PHC2
Bit 1
PHC1
Bit 0
PHC0
Port C Pull_hi Control Bits
0 = Pull_hi disable
1 = Pull_hi enable
(37) PDPHR: R96
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
PHD3
Bit 2
PHD2
Bit 1
PHD1
Bit 0
PHD0
PDPHR
Port D Pull_hi Control Bits
0 = Pull_hi disable
1 = Pull_hi enable
(38) EEDATA(EEPROM data register.):R9A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEDATA EED7
EED6
EED5
EED4
EED3
EED2
EED1
EED0
(39) EEADR (EEPROM address register):R9B.
Bit 7
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEADR
EEAD6 EEAD5 EEAD4 EEAD3 EEAD2 EEAD1 EEAD0
(40) EECON (EEPROM control register 1):R9C.
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
Bit 1
WR
Bit 0
RD
EECON1
WRERR WREN
WRERR : EEPROM Write Error Flag Bit.
0 = The EEPROM write operation completed
1 = The EEPROM write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
WREN : EEPROM Write Enable Bit.
0 = Inhibits write to the data EEPROM
1 = Allows write cycles
WR : Write Control Bit.
0 = Write cycle to the data EEPROM is complete
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not clear) in software.)
RD : Read Control Bit.
0 = Does not initiate an EEPROM read.
1 = Initiates an EEPROM read (read takes once cycle. RD is cleared in hardware. The RD bit
can only be set (not clear) in software.)
(41) EECON2(EEPROM control register 2): R9D.
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
EECON2
Write only ; Read as “0”
When write data to the EEPROM must write 55/H to EECCON2, and writ AA/H to EECCON2 then
set WR bit; the EEPROM can write data inside for write each byte.
Preliminary
P.14
2010/8 Ver. 0.3
http://www.mxmcu.com.cn
MDTIC [ Micon Design Technology Corporation ]
