MPC89X51AE 参数 Datasheet PDF下载

IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.

{IPH.x , IP.x}

11

10

01

00

Priority

Level

1 (highest)

2

3

4

SFR:

XICON

(External

Interrupt Control):

Bits-7

PX3

Bits-6

EX3

Bits-5

IE3

Bits-4

IT3

Bits-3

PX2

Bits-2

EX2

Bits-1

IE2

Bits-0

IT2

PX3:

If set, Set priority for external interrupt 3 higher

EX3:

If set, Enables external interrupt 3.

IE3:

Interrupt 3 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when

interrupt processed.

IT3:

Interrupt 3 type control bits. Set/Cleared by software to specified falling edge/low level triggered

interrupt.

PX2:

If set, Set priority for external interrupt 3 higher

EX2:

If set, enables external interrupt 2.

IE2:

Interrupt 2 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when interrupt

processed.

IT2:

Interrupt 2 types control bits. Set/Cleared by software to specify falling edge/low level triggered

interrupt.

Watchdog Timer

CLK/12

8

8-bit pre-scalar timer

15-bit WDT

RESET

ENW

IDLE

WIDL

PS0

PS1

PS2

CLRW

22

MPC89x51A Data Sheet

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