SFR:
WDTCR
(Watchdog
Timer Control):
Bits-7
-
Bits-6
-
Bits-5
ENW
Bits-4
CLRW
Bits-3
WIDL
Bits-2
PS2
Bits-1
PS1
Bits-0
PS0
ENW:
Enable WDT while it is set. ENW cannot be cleared by firmware.
1: = enable watchdog timer, 0: = does not use watchdog timer
CLRW:
Clear WDT to recount while it is set. Hardware will automatically clear this bits.
WIDL:
Set this bits to disable WDT generating reset even though the
μC
is in idle mode.
{PS2, PS1, PS0}:
select the pre-scalar output.
{0,
0, 0}:
= set the pre-scaling value 2
{0,
0, 1}:
= set the pre-scaling value 4
{0,
1, 0}:
= set the pre-scaling value 8
{0,
1, 1}:
= set the pre-scaling value 16
{1,
0, 0}:
= set the pre-scaling value 32
{1,
0, 1}:
= set the pre-scaling value 64
{1,
1, 0}:
= set the pre-scaling value 128
{1,
1, 1}:
= set the pre-scaling value 256
Serial IO Port (UART)
The serial port of MPC89x51A is duplex. It can transmit and receive simultaneously. The
receiving and transmitting of the serial port share the same SFR
SBUF,
but actually there are
two SBUF registers implemented in the chip, one is for transmitting and the other is for receiving.
The serial port can be operated in 4 different modes.
Mode 0
Generally, this mode purely is used to extend the I/O features of this device.
Operating under this mode, the device receives the serial data or transmits the serial data via pin
RXD, while there is a clock stream shifted via pin TXD which makes convenient for external
synchronization. An 8-bits data is serially transmitted/received with LSB first. The baud rate is
fixed at 1/12 the oscillator frequency.
Mode1
A 10-bitsdata is serially transmitted through TXD or received through RXD. The frame data
includes a start bits (0), 8 data bits and a stop bits (1). After the receiving, the device will keep the
stop bits in
RB8
which from SRF
SCON.
Baud Rate (for Mode 1)
=
2
SMOD
32
X
(Timer-1 overflow rate)
or =
(Timer-2 overflow rate)
16
MEGAWIN
MPC89x51A Data Sheet
23
MEGAWIN [ MEGAWIN TECHNOLOGY CO., LTD ]
