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MLX90401KDF 参数 Datasheet PDF下载

MLX90401KDF图片预览
型号: MLX90401KDF
PDF下载: 下载PDF文件 查看货源
内容描述: 直流无刷电机控制器 [Brushless DC Motor Controller]
分类和应用: 光电二极管电机控制器
文件页数/大小: 13 页 / 617 K
品牌: MELEXIS [ Melexis Microelectronic Systems ]
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MLX90401
Brushless DC Motor Controller
5 Absolute maximum ratings
Parameter
Supply Voltage, V
DD
(operating)
Output Voltage on pins Gate & Cap Boost
Voltage on Pins 17,18,20,21,23,24
Power Dissipation, P
D
Operating Temperature Range, T
A
Storage Temperature Range, T
S
Absolute maximum value
-0.3 to 45V
60V
-0.3 to 60V
500mW
-40 to 125°C
-40 to 125°C
Table 2: Absolute maximum ratings
6 MLX90401 electrical specifications
DC Operating Parameters T
A
= -40
o
C to 125
o
C
Parameter.
Supply voltage
Supply current
Output voltage
Output current
Undervoltage
Oscillator frequency
High state
Low state
High state input current
Low state input current
100% PWM state
0% PWM
1
Disable
1
High state input current
Low state input current
Debounce time (60°/120°
Select, Fwd/Rev)
Debounce time (/Brake)
2
Delay after start-up
Output current
1
Symbol
V
DD
I
DD
V
REF
I
REF
V
UV
f
OSC
V
IH
V
IL
I
IH
I
IL
Test Conditions
Operating
Operating
Voltage reference
Min
8
Typ
12-24
20
12
Max
44
35
15
10
Units
V
mA
V
mA
V
8
Undervoltage
Operating
Oscillator
Operating, R
OSC
=10kOhm,
C
OSC
=5nF
Logic inputs (Pins 2-6, 9, 11)
8
22
3.5
1.5
1.0
2.0
25
28
kHz
V
V
mA
mA
%Vref
%Vref
%Vref
mA
mA
ms
ms
ms
uA
Disable input (Pin 7)
V
100%PWM
V
0%PWM
V
DISABLE
I
IHDIS
I
ILDIS
Debouncing
t
delay1
t
delay2
t
delay3
Charge pumps
I
OCP
100
18
2.0
18.6
25
3.2
25.6
35
4.4
35.6
64.3
35.7
16
1.0
1.0
t
delay1
and t
delay2
depend on f
osc
and timing of the signals to be debounced. 60°/120° Select and Fwd/Rev
are debounced using a clock with a frequency of 256*f
osc
. /Brake is debounced using a clock with a
frequency of 32*f
osc
. Debouncing takes between 2 and 3 clock cycles. Typical example for, say 60°/120°
Select: 2.5*256*1/f
osc
= 2.5*256*1/25kHz = 25.6 ms.
3
t
delay3
depends on f
osc
. Precautions are taken that t
delay3
is
always
larger than t
delay1
, so that there are only
output signals when the chip is in the correct state.
3901090401
Rev 005
Page 4 of 13
Data sheet
Oct/05
2
Input levels of the DISABLE pin are defined internally by a resistor tree.