ML2036
PIN CONFIGURATION
ML2036
14-Pin PDIP (P14)
VSS 1
PDN-INH 2
CLK OUT 1 3
CLK OUT 2 4
SCK 5
SID 6
LATI 7
14 CLK IN
13 GAIN
12 DGND
11 AGND
10 VOUT
9
8
VREF
VCC
NC
VSS
PDN-INH
CLK OUT 1
CLK OUT 2
SCK
SID
LATI
ML2036
16-Pin Wide SOIC (S16W)
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
CLK IN
GAIN
NC
DGND
AGND
VOUT
VREF
VCC
TOP VIEW
PIN DESCRIPTION
(Pin Number in Parentheses is for SOIC Version)
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1 (2)
2 (3)
V
SS
P
DN
-INH
Negative supply (-5V).
Three level input which controls
the inhibit and power down
modes. Current source pull-up to
V
CC
.
Digital clock output from the
internal clock generator that can
drive other devices at f
CLK OUT 1
=
f
CLK IN
/2.
Digital clock output from the
internal clock generator that can
drive other devices at f
CLK OUT 2
=
f
CLK IN
/8.
Serial clock. Digital input which
clocks in serial data on its rising
edges.
Serial input data which programs
the frequency of V
OUT
.
Digital input which latches serial
data into the internal data latch on
falling edges.
8 (9)
9 (10)
V
CC
V
REF
Positive supply (5V).
Reference input. The voltage on
this pin determines the peak-to-
peak swing of V
OUT
. V
REF
can be
tied to V
CC
.
Analog output.
Analog ground. All analog inputs
and outputs are referenced to this
point.
Digital ground. All digital inputs
and outputs are referenced to this
point.
Sets V
OUT
peak amplitude to V
REF
or V
REF
/2. Current source pull-
down to DGND.
Clock input. The internal clock can
be generated by tying a 3 to
12MHz crystal from this pin to
DGND, or by applying a digital
clock signal directly to the pin.
3 (4)
CLK OUT 1
10 (11) V
OUT
11 (12) AGND
4 (5)
CLK OUT 2
12 (13) DGND
5 (6)
SCK
13 (15) GAIN
6 (7)
7 (8)
SID
LATI
14 (16) CLK IN
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
