ML6695
PIN CONFIGURATION
ML6695
44-Pin PLCC (Q44)
TSM0
TSM1
TSM2
TSM3
TSM4
AGND1
TXC
AVCC1
LPBK
AVCC2
AGND2
6 5 4 3 2 1 44 43 42 41 40
PWRDN
RSM4
RSM3
DGND1
RSM2
DVCC1
RSM1
DGND2
RSM0
RXC
DGND3
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
39
38
37
36
35
34
33
32
31
30
29
IOUT
IOUT
AGND3
RTSET
AVCC3A
AVCC3B
AVCC4A
AGND4A
AVCC4B
VIN+
VIN–
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
2
A
GND
1
TSM4
Analog ground
Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXCLK .
Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXC.
Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXC.
SDO
DVCC2
DGND4C
DGND4B
DGND4A
DVCC5
DGND5B
DGND5A
CAPDC
CAPB
AGND4B
TOP VIEW
5
TSM1
Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of TXC.
Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of TXC.
Powerdown TTL input. Driving this
pin low, or floating the pin, powers
the ML6695 down to a low-
current, inoperative state. Driving
PWRDN
high enables the
ML6695.
Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
6
TSM0
3
TSM3
7
PWRDN
4
TSM2
8
RSM4
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
