24AA512/24LC512/24FC512
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.8V to 5.5V
Automotive (E):
V
CC
= +2.5V to 5.5V
Characteristic
Clock frequency
Min.
—
—
—
4000
600
500
4700
1300
500
—
—
—
—
—
4000
600
250
4700
600
250
0
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
—
—
—
4700
1300
500
—
—
1,000,000
Max.
100
400
1000
—
—
—
—
—
—
1000
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
900
400
—
—
—
50
5
—
Units
kHz
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
All except, 24FC512
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
1.8V
≤
V
CC
<
2.5V
2.5V
≤
V
CC
≤
5.5V
2.5V
≤
V
CC
≤
5.5V 24FC512
All except, 24FC512
—
25°C
AC CHARACTERISTICS
Param.
No.
Sym.
F
CLK
1
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
ns
5
6
T
F
SDA and SCL fall time
ns
ns
T
HD
:
STA
Start condition hold time
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
ns
14
T
BUF
Bus free time: Time the bus
must be free before a new trans-
mission can start
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
Endurance
ns
16
17
18
Note 1:
2:
3:
4:
T
SP
T
WC
—
ns
ms
cycles
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
©
2005 Microchip Technology Inc.
DS21754G-page 3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
