24AA65/24LC65/24C65
5.7
Security Options
The 24XX65 has a sophisticated mechanism for write
protecting portions of the array. This write-protect
function is programmable and allows the user to protect
0-15 contiguous 4K blocks. The user sets the security
option by sending to the device the starting block
number for the protected region and the number of
blocks to be protected. All parts will come from the
factory in the default configuration with the starting
block number set to 15 and the number of protected
blocks set to zero. THE SECURITY OPTION CAN BE
SET ONLY ONCE WITH A LENGTH GREATER THAN
ZERO.
To invoke the security option, a Write command is sent
to the device with the leading bit (bit 7) of the first
address byte set to a ‘1’ (Figure 8-1). Bits 1-4 of the first
address byte define the starting block number for the
protected region.
For example, if the starting block number is to be set to
5, the first address byte would be 1XX0101X. Bits 0, 5
and 6 of the first address byte are disregarded by the
device and can be either high or low. The device will
acknowledge after the first address byte. A byte of don’t
care bits is then sent by the master, with the device
acknowledging afterwards. The third byte sent to the
device has bit 7 (S/HE) set high and bit 6 (R) set low.
Bits 4 and 5 are don’t cares and bits 0-3 define the
number of blocks to be write-protected. For example, if
three blocks are to be protected, the third byte would be
10XX0011. After the third byte is sent to the device, it
will acknowledge and a Stop bit is then sent by the mas-
ter to complete the command.
If one of the security blocks coincides with the high
endurance block, the high endurance setting will take
precedence. Also, if the range of the security blocks
encompass the high endurance block when the secu-
rity option is set, the security block range will be set
accordingly, but the high endurance block will continue
to retain the high endurance setting. As a result, the
memory blocks preceding the high endurance block will
be set as secure sections.
During a normal write sequence, if an attempt is made
to write to a protected address, no data will be written
and the device will not report an error or abort the
command. If a Write command is attempted across a
secure boundary, unprotected addresses will be written
and protected addresses will not.
acknowledge the second, and then send a Stop bit to
end the sequence. The upper four bits of both of these
bytes will always be read as ‘1’s. The lower four bits of
the first byte contains the starting secure block. The
lower four bits of the second byte contains the number
of secure blocks. The default starting secure block is
fifteen and the default number of secure blocks is zero
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W =
0).
If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 6-1 for flow
diagram.
FIGURE 6-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W =
0
5.8
Security Configuration Read
Did Device
Acknowledge
(ACK = 0)?
YES
Next
Operation
NO
The status of the secure portion of memory can be read
by using the same technique as programming this
option except the read bit (bit 6) of the configuration
byte is set to a one. After the configuration byte is sent,
the device will acknowledge and then send two bytes of
data to the master just as in a normal read sequence.
The master must acknowledge the first byte and not
DS21073J-page 10
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
