PIC16C63A/65B/73B/74B
4.2
Data Memory Organization
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this data sheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
RP1:RP0 (STATUS<6:5>)
= 00→ Bank0
= 01→ Bank1
= 10→ Bank2
Accessing a location above 0FFFh will cause a wrap-
around.
= 11→ Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 4-1:
PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
All implemented banks contain SFRs. Frequently used
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
PC<12:0>
13
Note: Maintain the IRP and RP1 bits clear in
CALL,RETURN
RETFIE,RETLW
these devices.
4.2.1
GENERAL PURPOSE REGISTER
FILE
Stack Level 1
The register file can be accessed either directly, or indi-
rectly, through the File Select Register (FSR)
(Section 4.5).
Stack Level 8
RESET Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
0800h
On-chip Program
Memory (Page 1)
0FFFh
1000h
1FFFh
2000 Microchip Technology Inc.
DS30605C-page 15
MICROCHIP [ MICROCHIP ]
