PIC18F6390/6490/8390/8490
To set up a Synchronous Slave Reception:
17.4.2
AUSART SYNCHRONOUS
SLAVE RECEPTION
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
2. If interrupts are desired, set enable bit, RC2IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
If receive is enabled by setting the CREN bit prior to
entering Sleep, or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register; if the RC2IE enable bit is set, the
interrupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
5. Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
6. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG2 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR3
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IF
TX2IE
TX2IP
CREN
RBIE
—
TMR0IF
—
INT0IF
—
RBIF
—
59
61
61
61
63
63
63
63
—
—
LCDIF
LCDIE
LCDIP
RX9
RC2IF
RC2IE
RC2IP
SREN
PIE3
—
—
—
—
IPR3
—
—
—
—
—
RCSTA2
RCREG2
TXSTA2
SPBRG2
SPEN
ADDEN
FERR
OERR
RX9D
AUSART2 Receive Register
CSRC TX9 TXEN
SYNC
—
BRGH
TRMT
TX9D
AUSART2 Baud Rate Generator Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS39629C-page 230
© 2007 Microchip Technology Inc.
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