256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Read Specifications
Figure 35: Synchronous Burst Mode 4-Word Read
tAVCH
Latency count
tAVQV
tVLCH tCHAX
CLK
tAVVH
A
A
tVHAX
tVHVL
tELVH
ADV#
tELCH
tELQV
tELQV
CE#
OE#
tCHTX
tGLTV
tCHTV
tCHQV
tCHTX
WAIT
DQ
tCHQV
tCHQX
tGLQV
tGLQX
tCHQX
Q0
Q1
Q2
Q3
1. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT as-
serted during initial latency and deasserted during valid data (RCR.10 = 0, WAIT asserted
low).
Note:
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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