256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Write Specifications
Figure 39: Synchronous Read to Write Timing
t
AVCH
Latency count
t
t
VLCH CHAX
CLK
t
AVQV
t
t
t
AVVH
WHAV
AVWH
A
t
VHVL
t
VHAX
t
ELVH
t
VLVH
ADV#
t
t
EHEL
ELCH
t
ELQV
t
t
EHTZ
WHEH
CE#
OE#
t
t
EHQZ
GLQV
t
VHWL
t
VHWL
t
CHWL
VLWH
t
t
t
WHAX
CHWL
ELWL
t
t
t
WHWL
WLWH
WE#
t
t
GLTX
CHTX
t
CHTV
WAIT
t
t
t
WHDX
CHQX
GLQX
t
CHQV
Q
DQ
D
D
1. WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.
10=0, WAIT asserted low). Clock is ignored during write operation.
Note:
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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