512Mb, 1Gb, 2Gb: P30-65nm
AC Read Specifications
Figure 27: Asynchronous Single-Word Read (ADV# LOW)
t
AVAV
t
AVQV
A
ADV#
t
ELQV
t
EHQZ
CE#
t
GLQV
t
GHQZ
OE#
t
GLTV
t
GHTZ
WAIT
t
GLQX
t
ELQX
DQ
t
PHQV
RST#
Note:
1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted
LOW).
Figure 28: Asynchronous Single-Word Read (ADV# Latch)
t
AVAV
t
AVQV
A[MAX:5]
A[4:1]
t
AVVH
t
VHVL
t
VHAX
ADV#
t
ELQV
t
EHQZ
CE#
t
GLQV
t
GHQZ
OE#
t
GLTV
t
GHTZ
WAIT
t
GLQX
t
ELQX
t
OH
DQ
Note:
1. WAIT shown deasserted during asynchronous read mode (RCR10 = 0, WAIT asserted
LOW).
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
80
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