512Mb, 1Gb, 2Gb: P30-65nm
AC Read Specifications
Figure 30: Synchronous Single-Word Array or Nonarray Read
t
AVCH
t
CHAX
CLK
t
AVQV
A
t
VHVL
t
AVVH
t
VLVH
t
VHAX
ADV#
t
ELCH
t
ELVH
t
ELQV
t
EHQZ
CE#
t
GLQX
t
GHQZ
OE#
t
GLTX
t
CHTV
t
CHTX
t
GHTZ
WAIT
t
GLQV
t
CHQV
t
CHQX
DQ
Notes:
1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be
configured to assert either during or one data cycle before valid data.
2. In this example, an
n-word
burst is initiated to the flash memory array and is terminated
by CE# deassertion after the first word in the burst.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
82
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