512Mb, 1Gb, 2Gb: P30-65nm
Signal Descriptions
Table 4: TSOP and Easy BGA Signal Descriptions (Continued)
Symbol
Type
Name and Function
WAIT
Output
Wait: Indicates data valid in synchronous array or non-array burst reads. Read configura-
tion register bit 10 (RCR.10, WT) determines its polarity when asserted. This signal's active
output is VOL or VOH when CE# and OE# are VIL. WAIT is High-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, this signal indicates invalid data when as-
serted and valid data when de-asserted.
• In asynchronous page mode, and all write modes, this signal is de-asserted.
VCC
Power
Device core power supply: Core (logic) source voltage. Writes to the array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
VSS
Power
Power
—
Output power supply: Output-driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
RFU
Reserved for future use: Reserved by Micron for future device functionality and en-
hancement. These should be treated in the same way as a DU signal.
DU
NC
—
—
Do not use: Do not connect to any other signal, or power supply; must be left floating.
No connect: No internal connection; can be driven or floated.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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