512Mb, 1Gb, 2Gb: P30-65nm
Bus Operations
ured over any 5ms time interval, 5μs after CE# is de-asserted. During standby, average
current is measured over the same time interval 5μs after CE# is de-asserted.
When the device is deselected (while CE# is de-asserted) during a PROGRAM or ERASE
operation, it continues to consume active power until the PROGRAM or ERASE opera-
tion is completed.
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
device if it is the system boot device. If a CPU reset occurs with no device reset, improp-
er CPU initialization may occur because the device may be providing status informa-
tion rather than array data. Micron devices enable proper CPU initialization following a
system reset through the use of the RST# input. RST# should be controlled by the same
low-true reset signal that resets the system CPU.
After initial power-up or reset, the device defaults to asynchronous read array mode,
and the status register is set to 0x80. Asserting RST# de-energizes all internal circuits,
and places the output drivers in High-Z. When RST# is asserted, the device shuts down
the operation in progress, a process which takes a minimum amount of time to com-
plete. When RST# has been de-asserted, the device is reset to asynchronous read array
state.
When device returns from a reset (RST# de-asserted), a minimum wait is required be-
fore the initial read access outputs valid data. Also, a minimum delay is required after a
reset before a write cycle can be initiated. After this wake-up interval passes, normal op-
eration is restored.
Note:
If RST# is asserted during a PROGRAM or ERASE operation, the operation is ter-
minated and the memory contents at the aborted location (for a program) or block (for
an erase) are no longer valid, because the data may have been only partially written or
erased.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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