512Mb, 1Gb, 2Gb: P30-65nm
Read Operations
Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a re-
set. Under asynchronous page mode, the device can also perform single word read. The
read configuration register must be configured to enable synchronous burst reads of the
array.
The device can be in any of four read states: read array, read identifier, read status, or
read CFI. Upon power-up, or after a reset, the device defaults to read array. To change
the read state, the appropriate READ command must be written to the device.
Asynchronous Single Word Read
To perform an asynchronous single word read, an address is driven onto the address
bus, and CE# is asserted.
Note:
To perform an asynchronous single word read for a TSOP package, ADV# must be
LOW throughout the READ cycle. For an Easy BGA package, ADV# can be driven HIGH
to latch the address or be held LOW throughout the READ cycle.
WE# and RST# must already have been de-asserted. WAIT is set to a de-asserted state
during single word mode, as determined by bit 10 of the read configuration register.
CLK is not used for asynchronous single word reads, and is ignored. If asynchronous
reads are to be performed only, CLK should be tied to a valid V
IH
or V
SS
level, WAIT can
be floated, and ADV# must be tied to ground. After OE# is asserted, the data is driven
onto DQ[15:0] after an initial access time
t
AVQV or
t
GLQV delay.
Asynchronous Page Mode Read (Easy BGA Only)
Note:
Asynchronous Page Mode Read is supported only in the main array.
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to read array. However, to perform array reads after any other
device operation (WRITE operation), the READ ARRAY command must be issued in or-
der to read from the array.
Asynchronous page mode reads can only be performed when read configuration regis-
ter bit RCR15 is set.
To perform an asynchronous page-mode read, an address is driven onto the address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been de-asser-
ted. WAIT is de-asserted during asynchronous page mode. ADV# can be driven HIGH to
latch the address, or it must be held LOW throughout the READ cycle. CLK is not used
for asynchronous page mode reads, and is ignored. If only asynchronous reads are to be
performed, CLK should be tied to a valid V
IH
or V
SS
level, WAIT signal can be floated,
and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial ac-
cess time
t
AVQV delay.
In asynchronous page mode, 16 data words are “sensed” simultaneously from the array
and loaded into an internal page buffer. The buffer word corresponding to the initial
address on the address bus is driven onto DQ[15:0] after the initial access delay. The
lowest four address bits determine which word of the 16-word page is output from the
data buffer at any given time.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
24
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