Micron M25P40 Serial Flash Embedded Memory
WRITE STATUS REGISTER
WRITE STATUS REGISTER
The WRITE STATUS REGISTER command allows new values to be written to the status
register. Before the WRITE STATUS REGISTER command can be accepted, a WRITE EN-
ABLE command must have been executed previously. After the WRITE ENABLE com-
mand has been decoded and executed, the device sets the write enable latch (WEL) bit.
The WRITE STATUS REGISTER command is entered by driving chip select (S#) LOW,
followed by the command code and the data byte on serial data input (DQ0). The
WRITE STATUS REGISTER command has no effect on b6, b5, b1 and b0 of the status
register. The status register b6 and b5 are always read as ‘0’. S# must be driven HIGH
after the eighth bit of the data byte has been latched in. If not, the WRITE STATUS REG-
ISTER command is not executed.
Figure 12: WRITE STATUS REGISTER Command Sequence
0
C
7
8
9
10
11
12
13
14
15
LSB
DQ0
MSB
Command
D
IN
MSB
D
IN
D
IN
D
IN
D
IN
D
IN
D
IN
D
IN
LSB
D
IN
As soon as S# is driven HIGH, the self-timed WRITE STATUS REGISTER cycle is initi-
ated; its duration is t
W
. While the WRITE STATUS REGISTER cycle is in progress, the sta-
tus register may still be read to check the value of the write in progress (WIP) bit. The
WIP bit is 1 during the self-timed WRITE STATUS REGISTER cycle, and is 0 when the
cycle is completed. Also, when the cycle is completed, the WEL bit is reset.
The WRITE STATUS REGISTER command allows the user to change the values of the
block protect bits (BP2, BP1, BP0). Setting these bit values defines the size of the area
that is to be treated as read-only, as defined in the Protected Area Sizes table.
The WRITE STATUS REGISTER command also allows the user to set and reset the status
register write disable (SRWD) bit in accordance with the write protect (W#/V
PP
) signal.
The SRWD bit and the W#/V
PP
signal allow the device to be put in the HARDWARE PRO-
TECED (HPM) mode. The WRITE STATUS REGISTER command is not executed once
the HPM is entered. The options for enabling the status register protection modes are
summarized here.
Table 7: Status Register Protection Modes
Memory Content
W#/V
PP
Signal
1
0
1
SRWD
Bit
0
0
1
Protection
Mode (PM)
SOFTWARE
PROTECTED mode
(SPM)
Status Register
Write Protection
Software protection
Protected
Area
Commands not
accepted
Unprotected
Area
Commands
accepted
Notes
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
24
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