4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
what commands are allowed in this condition. See the
Command Execution section for more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F004B3 and MT28F400B3 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to V
SS
±0.2V. In this mode, the current
draw is a maximum of 8µA at 3.3V V
CC
. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.
quires that a super-voltage (V
HH
) be applied to RP# or that
the WP# pin be driven HIGH before erasure is com-
menced. The boot block is intended for the core firmware
required for basic system functionality. The remaining
six blocks do not require either of these two conditions be
met before WRITE or ERASE operations.
BOOT BLOCK
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage (V
HH
)
of 12V or when the WP# pin is V
IH
. During a WRITE or
ERASE of the boot block, the RP# pin must be held at V
HH
or the WP# pin held HIGH until the ERASE or WRITE is
completed. The V
PP
pin must be at V
PPH
(3.3V or 5V) when
the boot block is written to or erased.
The MT28F004B3 and MT28F400B3 are available in
two configurations and top or bottom boot block. The top
boot block version supports processors of the x86 variety.
The bottom boot block version is intended for 680X0 and
RISC applications. Figure 1 illustrates the memory ad-
dress maps associated with these two versions.
MEMORY ARCHITECTURE
The MT28F004B3 and MT28F400B3 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into seven addressable blocks that vary in size
and are independently erasable. When blocks rather than
the entire array are erased, total device endurance is
enhanced, as is system flexibility. Only the ERASE func-
tion is block-oriented. All READ and WRITE operations
are done on a random-access basis.
The boot block is protected from unintentional ERASE
or WRITE with a hardware protection circuit which re-
WORD ADDRESS BYTE ADDRESS
3FFFFh
7FFFFh
WORD ADDRESS
3FFFFh
3E000h
3DFFFh
3D000h
3CFFFh
3C000h
3BFFFh
BYTE ADDRESS
7FFFFh
16KB Boot Block
128KB Main Block
30000h
2FFFFh
60000h
5FFFFh
7C000h
7BFFFh
7A000h
79FFFh
78000h
77FFFh
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
30000h
2FFFFh
60000h
5FFFFh
20000h
1FFFFh
40000h
3FFFFh
128KB Main Block
128KB Main Block
20000h
1FFFFh
40000h
3FFFFh
10000h
0FFFFh
20000h
1FFFFh
128KB Main Block
96KB Main Block
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
10000h
0FFFFh
20000h
1FFFFh
8KB Parameter Block
8KB Parameter Block
16KB Boot Block
128KB Main Block
00000h
00000h
Bottom Boot
MT28F004B3/400B3xx-xxB
Top Boot
MT28F004B3/400B3xx-xxT
Figure 1
Memory Address Maps
4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
