4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
SELF-TIMED WRITE SEQUENCE
COMPLETE WRITE STATUS-CHECK
SEQUENCE
1
(WORD OR BYTE WRITE)
Start (WRITE completed)
Start
NO
NO
4, 5
SR3 = 0?
YES
V
PP Error
WRITE 40h or 10h
5
SR4 = 0?
YES
BYTE/WORD WRITE Error
VPP = 5V
WRITE Successful
WRITE Word or Byte
Address/Data
STATUS REGISTER
READ
NO
SR7 = 1?
YES
2
Complete Status
Check (optional)
3
WRITE Complete
NOTE: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.
2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is
cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
or ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
4MbSmart3BootBlockFlashMemory
F45_3.p65 – Rev. 3, Pub. 12/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
15
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