4Mb
SMART 3 BOOT BLOCK FLASH MEMORY
1
SELF-TIMED BLOCK ERASE SEQUENCE
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
Start (ERASE completed)
Start
NO
YES
NO
5, 6
VPP Error
WRITE 20h
SR3 = 0?
YES
VPP = 3.3V or 5V
6
SR4, 5 = 1?
NO
Command Sequence Error
WRITE D0h,
Block Address
6
SR5 = 0?
BLOCK ERASE Error
YES
STATUS REGISTER
READ
ERASE Successful
NO
NO
SR7 = 1?
YES
Suspend ERASE?
YES
4
2
Suspend
Sequence
Complete Status
Check (optional)
ERASE Resumed
3
ERASE Complete
NOTE: 1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is
cleared.
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE
or ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
4MbSmart3BootBlockFlashMemory
F45_3.p65 – Rev. 3, Pub. 12/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
16
MICRON [ MICRON TECHNOLOGY ]
