8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
Commands are issued to bring the device into differ-
entoperationalmodes. Eachmodeallowsspecificopera-
tions to be performed. Several modes require a sequence
of commands to be written before they are reached. The
following section describes the properties of each mode,
and Table 3 lists all command sequences required to
perform the desired operation.
WRITE SEQUENCE
Two consecutive cycles are needed to input data to
the array. WRITE SETUP (40h or 10h) is given in the first
cycle. The next cycle is the WRITE, during which the write
address and data are issued and VPP is brought to VPPH.
Writing to the boot block also requires that the RP# pin be
brought to VHH or the WP# pin be brought HIGH at the
same time VPP is brought to VPPH. The ISM now begins to
write the word or byte. VPP must be held at VPPH until the
WRITE is completed (SR7 = 1).
While the ISM executes the WRITE, the ISM status bit
(SR7) is at 0, and the device does not respond to any
commands. Any READ operation produces the status
register contents on DQ0–DQ7. When the ISM status bit
(SR7) is set to a logic 1, the WRITE has been completed,
and the device goes into the status register read mode
until another command is given.
READ ARRAY
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFh) must be given to return
to the array read mode. Unlike the WRITE SETUP com-
mand (40h), READ ARRAY does not need to be given
before each individual READ access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90h) may be written to the CEL to
enter the identify device mode. While the device is in this
mode, anyREADproducesthedeviceidentificationwhen
A0 is HIGH and the manufacturer compatibility identifi-
cation when A0 is LOW. The device remains in this mode
until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the part.
Doing either during a WRITE corrupts the data being
written. If only the WRITE SETUP command has been
given, the WRITE may be nullified by performing a null
WRITE. To execute a null WRITE, FFh must be written
Table 3
Command Sequences
BUS
CYCLES
FIRST
CYCLE
SECOND
CYCLE
COMMANDS
REQ’D OPERATION ADDRESS DATA OPERATIONADDRESS DATA NOTES
READ ARRAY
1
3
2
1
2
2
2
2
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
X
X
X
X
X
X
X
X
FFh
90h
70h
50h
20h
B0h
40h
10h
1
2, 3
4
IDENTIFY DEVICE
READ
READ
IA
X
ID
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
SRD
WRITE
WRITE
WRITE
WRITE
BA
X
D0h
D0h
WD
WD
5, 6
WA
WA
6, 7
6, 7
ALTERNATE WORD/BYTE
WRITE
NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable Flash array READ cycles.
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. BA = Block Address (A12–A19).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
8MbSmart3BootBlockFlashMemory
Q10_3.p65 – Rev. 3, Pub. 10/01
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2001,MicronTechnology,Inc.
12
MICRON [ MICRON TECHNOLOGY ]
