ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1–A7 when the burst length is set to two, by
A2–A7 when the burst length is set to four, and by A3–
A7 when the burst length is set to eight. The remaining
(least significant) address bit(s) are used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.
Table 1
Burst Definition
Burst
Length
StartingColumn
Address
OrderofAccessesWithinaBurst
Type=Sequential
Type=Interleaved
A0
0
1
0-1
1-0
0-1
1-0
2
4
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Figure 1
Mode Register Definition
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn,Cn+1,Cn+2
Cn+3,Cn+4...
…Cn-1,
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
A1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A0
Address Bus
8
1
11 10
9
8
6
5
4
1
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
*Program M11,
M10 = “0, 0” to
ensure compatibility
with future devices.
Burst Length
Full
Page
256
n = A0–A7
M2 M1 M0
M3 = 0
M3 = 1
Notsupported
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
(location0-255)
Cn...
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
NOTE: 1. For a burst length of two, A1–A7 select the block-
of-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2–A7 select the block-
of-four burst; A0–A1 select the starting column
within the block.
3. For a burst length of eight, A3–A7 select the
block-of-eight burst; A0–A2 select the starting
column within the block.
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5 M4
4. For a full-page burst, the full row is selected and
A0–A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0–A7 select the unique
column to be accessed, and mode register bit M3
is ignored.
Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
Reserved
Reserved
Reserved
Reserved
7. Burst write (x32: 1, 2, 4, or 8 Dwords, x16: 1, 2, 4,
or 8 words) is supported (not full page).
8. The contents of the mode register can be read
usingtheREADDEVICECONFIGURATIONcommand
(004h).
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
NOTE: 1. A11 and M11 are supported only by 4 Meg x 16 configuration.
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
11
MICRON [ MICRON TECHNOLOGY ]
