ADVANCE
64Mb: x16, x32
SYNCFLASH MEMORY
PIN AND BALL DESCRIPTIONS
TSOP PIN FBGA BALL
NUMBERS NUMBERS SYMBOL
68
J1
CLK
TYPE
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SyncFlash memory
input signals are sampled on the positive edge of CLK. CLK also
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides STANDBY opera-
tion or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down
modes, where CKE becomes asynchronous until after exiting
the same mode. The input buffers, including CLK, are disabled
during power-down modes, providing low standby power.
CKE may be tied HIGH in systems where power-down modes
(other than RP# deep power-down) are not required.
Chip Select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
Command Inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
Input/Output Mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQM is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (after a
two-clock latency) when DQM is sampled HIGH during a READ
cycle. For x16, DQM0 corresponds to DQ0–DQ7, DQM1
corresponds to DQ8–DQ15. For x32, DQM0 corresponds to
DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corre-
sponds to DQ16–DQ23, DQM3 corresonds to DQ24–DQ31.
DQM0–DQM3 are in the same state when referenced as DQM.
Address Inputs: A0–A11 are sampled during the ACTIVE
command (row address A0–A11 [x16]; A0–A10 [x32]) and
READ/WRITE command (column-address A0–A7) to select one
location in the respective bank. The address inputs provide the
op-code during a LOAD MODE REGISTER command and the
com-code during an LCR command. For x16: A11 is pin 66 (J3),
and A9 is pin 70 (K3).
Bank Address Input(s): BA0, BA1 define to which bank the
ACTIVE, READ, or WRITE command is being applied.
67
J2
CKE
Input
20
J8
CS#
Input
19, 18, 17
16, 71
J9, K7, K8
K9, K1
RAS#,
CAS#, WE#
x16: DQM0,
DQM1
Input
Input
16, 71, 28,
59
K9, K1, F8, x32: DQM0
F2
–DQM3
25–27,
G8, G9, F7,
60–66, 24, F3, G1, G2,
70
G3, H1, H2,
J3, K3, G7
A0–A11
Input
22, 23
J7, H8
BA0, BA1
Input
(continued on next page)
64Mb: x16, x32 SyncFlash
MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
