1Gb: x4, x8, x16 DDR3 SDRAM
Features
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REFRESH to Power-Down Entry .................................................................................................. 188
ACTIVATE to Power-Down Entry ................................................................................................. 189
PRECHARGE to Power-Down Entry ............................................................................................. 189
MRS Command to Power-Down Entry ......................................................................................... 190
Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 190
RESET Sequence ......................................................................................................................... 192
On-Die Termination ................................................................................................................... 193
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 198
Dynamic ODT: Without WRITE Command .................................................................................. 198
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 199
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 200
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 200
Synchronous ODT ...................................................................................................................... 202
Synchronous ODT (BC4) ............................................................................................................. 203
ODT During READs .................................................................................................................... 205
Asynchronous ODT Timing with Fast ODT Transition .................................................................. 207
Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 209
Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 211
Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 213
Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 213
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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