Advance
576Mb: x18, x36 RLDRAM 3
AUTO REFRESH Command
AUTO REFRESH Command
The RLDRAM 3 device uses two unique AUTO REFRESH (AREF) command protocols,
bank address-controlled AREF and multibank AREF. The desired protocol is selected by
setting MR1[8] LOW (for bank address-controlled AREF) or HIGH (for multibank AREF)
during an MRS command. Bank address-controlled AREF is identical to the method
used in RLDRAM2 devices, whereby banks are refreshed independently. The value on
bank addresses BA[3:0], issued concurrently with the AREF command, define which
bank is to be refreshed. The array address is generated by an internal refresh counter,
effectively making each address bit a "Don't Care" during the AREF command. The de-
lay between the AREF command and a subsequent command to the same bank must be
at least tRC.
Figure 39: Bank Address-Controlled AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
Address
Bank
Address
BA[3:0]
Don’t Care
The multibank AREF protocol, enabled by setting bit MR1[8] HIGH during an MRS
command, enables the simultaneous refresh of a row in up to four banks. In this meth-
od, address balls A[15:0] represent banks [15:0], respectively. The row addresses are gen-
erated by an internal refresh counter for each bank; therefore, the purpose of the ad-
dress balls during an AREF command is only to identify the banks to be refreshed. The
bank address balls BA[3:0] are considered "Don't Care" during a multibank AREF com-
mand.
A multibank AUTO REFRESH is performed for a given bank when its corresponding ad-
dress ball is asserted HIGH during an AREF command. Any combination of up to four
address balls can be asserted HIGH during the rising clock edge of an AREF command
to simultaneously refresh a row in each corresponding bank. The delay between an
AREF command and subsequent commands to the banks refreshed must be at least
tRC. Adherence to tSAW must be followed when simultaneously refreshing multiple
banks. If refreshing three or four banks with the multibank AREF command, tMMD
must be followed. This specification requires two clock cycles between any bank com-
mand (READ, WRITE, AREF) to the multibank AREF or the multibank AREF to any bank
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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