Advance
576Mb: x18, x36 RLDRAM 3
INITIALIZATION Operation
INITIALIZATION Operation
The RLDRAM 3 device must be powered up and initialized in a predefined manner. Op-
erational procedures other than those specified may result in undefined operations or
permanent damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, VDD, VDDQ). Apply VDD and VEXT before, or at the same time as,
VDDQ. VDD must not exceed VEXT during power supply ramp. VEXT, VDD, VDDQ must
all ramp to their respective minimum DC levels within 200ms.
2. Ensure that RESET# is below 0.2 × VDDQ during power ramp to ensure the outputs
remain disabled (High-Z) and ODT is off (RTT is also High-Z). DQs, and QK signals
will remain High-Z until MR0 command. All other inputs may be undefined dur-
ing the power ramp.
3. After the power is stable, RESET# must be LOW for at least 200µs to begin the initi-
alization process.
4. After 100 or more stable input clock cycles with NOP commands, bring RESET#
HIGH.
5. After RESET# goes HIGH, a stable clock must be applied in conjunction with NOP
commands for 10,000 cycles.
6. Load desired settings into MR0.
7. tMRSC after loading the MR0 settings, load operating parameters in MR1, includ-
ing DLL Reset and Long ZQ Calibration.
8. After the DLL is reset and Long ZQ Calibration is enabled, the input clock must be
stable for 512 clock cycles while NOPs are issued.
9. Load desired settings into MR2. If using the RTR, follow the procedure outlined in
the READ Training Function – Back-to-Back Readout figure prior to entering nor-
mal operation.
10. The RLDRAM 3 is ready for normal operation.
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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