256Mb: x4, x8, x16 DDR SDRAM
State Diagram
State Diagram
Figure 1:
Simplified State Diagram
Power
applied
Power
on
PRE
Precharge
all
banks
LMR
Self
refresh
REFS
LMR
REFSX
Idle
REFA
all
banks
precharged
CKEL
CKEH
MR
EMR
Auto
refresh
Active
power-
down
ACT
CKE
HIGH
Precharge
power-
down
CKE
LOW
Row
active
WRITE
WRITE
WRITE A
Write
READ A
READ
READ
BST
READ
Burst
stop
Read
WRITE A
PRE
READ A
PRE
PRE
READ A
Write A
Read A
PRE
Precharge
PREALL
Automatic sequence
Command
sequence
ACT = ACTIVE
BST = BURST TERMINATE
CKEH
= Exit power-down
CKEL
= Enter power-down
EMR = Extended mode register
LMR = LOAD MODE REGISTER
MR = Mode register
PRE = PRECHARGE
PREALL = PRECHARGE all
banks
READ A = READ with auto precharge
REFA = AUTO REFRESH
REFS = Enter self refresh
REFSX = Exit self refresh
WRITE A = WRITE with auto precharge
Note:
This diagram represents operations within a single bank only and does not capture concur-
rent operations in other banks.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core1.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
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©2003 Micron Technology, Inc. All rights reserved.
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