256Mb: x4, x8, x16 DDR SDRAM
Functional Block Diagrams
Functional Block Diagrams
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory
containing 268,435,456 bits. It is internally configured as a 4-bank DRAM.
Figure 1:
64 Meg x 4 Functional Block Diagram
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
Command
decode
Control
logic
Bank 3
Bank 2
Bank 1
Mode registers
Refresh
counter
13
Row-
address
MUX
13
Bank 0
row-
address
latch
and
decoder
Bank 0
memory
array
(8192 x 1024 x 8)
4
8
4
CK
15
13
8192
Data
DLL
Sense amplifiers
READ
latch
MUX
4
Drivers
DQS
generator
Column 0
1
8192
DQ[3:0]
2
I/O gating
DM mask logic
Bank
control
logic
Input
registers
1
1
1
1
2
4
8
4
4
4
4
1
DQS
DQS
8
A[12:0],
BA[1:0]
15
Address
register
Mask
2
1024
(x8)
8
WRITE
FIFO
and
drivers
CK
out
CK
in
Rcvrs
DM
Column
decoder
Column-
address
counter/
latch
10
Data
11
CK
1
Column 0
1
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
9
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©2003 Micron Technology, Inc. All rights reserved.
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