PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
128MB DDR SDRAM PART NUMBERS
(Note: xx= -75, -75Z, or -8)
PART NUMBER
MT46V32M4TG-xx
MT46V32M4TG-xxL
MT46V16M8TG-xx
MT46V16M8TG-xxL
MT46V8M16TG-xx
MT46V8M16TG-xxL
CONFIGURATION
32 Meg x 4
32 Meg x 4
16 Meg x 8
16 Meg x 8
8 Meg x 16
8 Meg x 16
I/O DRIVE LEVEL
Full Drive
Full Drive
Full Drive
Full Drive
Programmable Drive
Programmable Drive
REFRESH OPTION
Standard
Low Power
Standard
Low Power
Standard
Low Power
GENERAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-
bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 128Mb DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding
n-bit
wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 128Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compatible.
NOTE 1:
The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
Additionally, the x16 is divided in to two bytes —
the lower byte and upper byte. For the lower byte
(DQ0 through DQ7) DM refers to LDM and DQS
refers to LDQS; and for the upper byte (DQ8 through
DQ15) DM refers to UDM and DQS refers to UDQS.
NOTE 2:
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
