PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 8
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTERS
REFRESH 12
COUNTER
12
12
ROW-
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
8
16
READ
LATCH
MUX
8
DQS
GENERATOR
COL0
8
CK
DATA
DLL
SENSE AMPLIFIERS
8192
DRVRS
1
DQ0 -
DQ7, DM
DQS
DQS
1
1
1
2
8
16
8
DATA
8
8
8
RCVRS
1
2
I/O GATING
DM MASK LOGIC
BANK
CONTROL
LOGIC
16
1
MASK
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
INPUT
REGISTERS
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
512
(x16)
16
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
10
CK
COL0
1
1
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
