ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
COMMANDS
Truth Table 1 provides a quick reference of avail-
able commands. This is followed by a verbal descrip-
tion of each command. Two additional Truth Tables
appear following the Operation section; these tables
provide current state/next state information.
TRUTH TABLE 1 – COMMANDS
(Note: 1)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
CS#
H
L
L
L
L
L
L
L
L
RAS#
X
H
L
H
H
H
L
L
L
CAS#
X
H
H
L
L
H
H
L
L
WE#
X
H
H
H
L
L
L
H
L
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
NOTES
9
9
3
4
4
8
5
6, 7
2
TRUTH TABLE 1A – DM OPERATION
(Note: 10)
NAME (FUNCTION)
Write Enable
Write Inhibit
DM
L
H
DQs
Valid
X
NOTES
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-
code to be written to the selected mode register.
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address (where
i
= 9 for x16, 9,11 for x8, and 9, 11, 12 for x4);
A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0-BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
