PRELIMINARY
‡
1Gb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
Features
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two
–one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
•
t
RAS lockout supported (
t
RAP =
t
RCD)
MT46V256M4 – 64 MEG X 4 X 4 BANKS
MT46V128M8 – 32 MEG X 8 X 4 BANKS
MT46V64M16 – 16 MEG X 16 X 4 BANKS
Figure 1: Pin Assignment (Top View)
66-pin TSOP
x4
x8
x16
V
DD
V
DD
V
DD
NC
DQ0
DQ0
V
DD
Q V
DD
Q
V
DD
Q
NC
DQ1
NC
DQ0
DQ1
DQ2
V
SS
Q
V
SS
Q
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
DQ5
DQ1
DQ3
DQ6
V
SS
Q
V
SS
Q
VssQ
NC
DQ7
NC
NC
NC
NC
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
LDQS
A13
A13
A13
V
DD
V
DD
V
DD
DNU
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
V
DD
V
DD
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
OPTIONS
• Configuration
256 Meg x 4 (64 Meg x 4 x 4 banks)
128 Meg x 8 (32 Meg x 8 x 4 banks)
64 Meg x 16 (16 Meg x 16 x 4 banks)
• Plastic Package – OCPL
66-pin TSOP(400 mil width, 0.65mm
pin pitch)
66-pin TSOP Lead-Free (400 mil width,
0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2.5 (DDR266B)
1, 2
• Temperature Rating
Commercial Temperature
(0
°
C to +70
°
C)
NOTE:
MARKING
Configuration
256 MEG X 4 128 MEG X 8 64 MEG X 16
64 Meg x 4 x 4
banks
8K
16K (A0–A13)
4(BA0,BA1)
4K(A0–A9,
A11, A12)
32 Meg x 8 x 4 16 Meg x 16 x 4
banks
banks
8K
8K
16K (A0–A13)
16K (A0–A13)
4(BA0,BA1)
4(BA0,BA1)
2K(A0–A9, A11)
1K(A0–A9)
256M4
128M8
64M16
TG
P
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
Key Timing Parameters
SPEED
GRADE
CLOCKRATE
CL=2**
CL=2.5**
DATA-OUT
WINDOW*
ACCESS
WINDOW
DQS–DQ
SKEW
-75
None
-75
100 MHz
133MHz
2.5ns
±0.75ns
+0.5ns
1. Supports PC2100 modules with 2.5-3-3 timing
2. Supports PC1600 modules with 2-2-2 timing,
* Minimum clock rate @ CL= 2.5
** CL = CAS (Read) Latency
09005aef8076894f
1gbBDDRx4x8x16_1.fm - Rev. A 3/03 EN
1
©2003 Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
MICRON [ MICRON TECHNOLOGY ]
