PRELIMINARY
1Gb : x4, x8, x16
DDR SDRAM
This device supports concurrent auto precharge such that when a read with auto pre-
charge is enabled or a write with auto precharge is enabled any command to other
banks is allowed, as long as that command does not interrupt the read or write data
transfer already in process. In either case, all other related limitations apply (e.g., con-
tention between read data and write data must be avoided).
b. The minimum delay from a read or write command with auto precharge enabled, to a com-
mand to a different bank is summarized below.
MINIMUM DELAY
FROM COMMAND
TO COMMAND
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
(WITH CONCURRENT AUTO PRECHARGE)
t
t
WRITE w/AP
[1 + (BL/2)] * CK + WTR
t
(BL/2) * CK
t
1 CK
t
ACTIVE
1 CK
t
READ w/AP
READ or READ w/AP
WRITE or WRITE w/AP
(BL/2) * CK
[CLRU + (BL/2)] *tCK
t
PRECHARGE
ACTIVE
1 CK
t
1 CK
NOTE:
CLRU = CAS Latency (CL) rounded up to the next integer
BL = Bust Length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to
end the READ burst prior to asserting a WRITE command.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
44
MICRON [ MICRON TECHNOLOGY ]
