PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 31: Input Voltage Waveform
V
DD
Q (2.3V minimum)
V
OH(MIN)
(1.670V1 for SSTL2 termination)
System Noise Margin (Power/Ground,
Crosstalk, Signal Integrity Attenuation)
1.560V
V
IH
AC
1.400V
V
IH
DC
1.300V
1.275V
1.250V
1.225V
1.200V
V
REF
+AC Noise
V
REF
+DC Error
V
REF
-DC Error
V
REF
-AC Noise
1.100V
V
IL
DC
0.940V
V
IN
AC - Provides margin
between
V
OL
(MAX)
and
V
ILAC
V
OL
(MAX)
(0.83V2 for SSTL2 termination)
V
IL
AC
Receiver
Transmitter
V
SS
Q
NOTE:
1. V
OH
(MIN) with test load is 1.927V
2. V
OL
(MAX) with test load is 0.373V
3. Numbers in diagram reflect nomimal
values utilizing circuit below.
V
TT
25
Ω
25
Ω
Reference
Point
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
