PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
40.
V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 1.5V for a
pulse width
£
3ns and the pulse width can not
be greater than
1/3
of the cycle rate. V
IL
under-
shoot: V
IL
(MIN) = -1.5V for a pulse width
£
3ns
and the pulse width can not be greater than
1/3
of the cycle rate.
41. V
DD
and V
DD
Q must track each other.
42. This maximum value is derived from the refer-
enced test load. In practice, the values obtained in
a typical terminated design may reflect up to
310ps less for
t
HZ (MAX) and the last DVW.
t
HZ
(MAX) will prevail over
t
DQSCK (MAX) +
t
RPST
(MAX) condition.
t
LZ (MIN) will prevail over
t
DQSCK (MIN) +
t
RPRE (MAX) condition.
43. For slew rates of greater than 1V/ns the (LZ) tran-
sition will start about 310ps earlier.
44. During initialization, V
DD
Q, V
TT
, and V
REF
must be
equal to or less than V
DD
+ 0.3V. Alternatively, V
TT
may be 1.35V maximum during power up, even if
V
DD
/V
DD
Q are 0V, provided a minimum of 42
W
of
series resistance is used between the V
TT
supply
and the input pin.
45. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
46. Not used.
47. Reserved for future use.
48. Random addressing changing 50 percent of data
changing at every transfer.
49. Random addressing changing 100 percent of data
changing at every transfer.
50. CKE must be active (HIGH) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
RFC has been satisfied.
51. I
DD
2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. I
DD
2Q is similar
to I
DD
2F except I
DD
2Q specifies the address and
control inputs to remain stable. Although I
DD
2F,
I
DD
2N, and I
DD
2Q are similar, I
DD
2F is “worst
case.”
52. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset fol-
lowed by 200 clock cycles before any Read com-
mand.
Figure 36: Reduced Drive Pull-Down
Characteristics
80
70
60
50
I
OUT
(mA)
40
30
20
10
0
0.0
0.5
1.0
V
OUT
(V)
1.5
2.
Figure 37: Reduced Drive Pull-Up
Characteristics
0
-10
-20
-30
I
OUT
(mA)
-40
-50
-60
-70
-80
0.0
0.5
1.0
V
DD
Q - V
OUT
(V)
1.5
2.0
2.5
39.
The voltage levels used are derived from a mini-
mum
V
DD
level and the referenced test load. In
practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
