PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 38: x4, x8 Data Output Timing –
t
DQSQ,
t
QH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP
5
tHP
5
tDQSQ
3
tHP
5
tDQSQ
3
tHP
5
tHP
5
tDQSQ
3
tHP
5
tDQSQ
3
DQS
1
DQ (Last data valid)
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQ
2
DQ (First data no longer valid)
tQH
4
tQH
4
tQH
4
tQH
4
DQ (Last data valid)
DQ (First data no longer valid)
T2
T2
T2n
T2n
T3
T3
T3n
T3n
All DQ and DQS, collectively
6
Earliest signal transition
Latest signal transition
T2
T2n
T3
T3n
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window
NOTE:
1. DQ transitioning after DQS transition define
t
DQSQ window. DQS transitions at T2 and at T2n are an “early DQS,” at
T3 is a “nominal DQS,” and at T3n is a “late DQS.”
2. For a x4, only two DQ apply.
3.
t
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last
valid DQ transition.
4.
t
QH is derived from
t
HP:
t
QH =
t
HP -
t
QHS.
5.
t
HP is the lesser of
t
CL or
t
CH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as
t
QH minus
t
DQSQ.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
