PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 49: Bank Write - With Auto Precharge
CK#
CK
t
IS
t
IH
t
CK
t
CH
t
CL
T0
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
CKE
t
IS
t
IH
ACT
t
IS
t
IH
Col
n
NOP5
WRITE2
NOP5
NOP5
NOP5
NOP5
NOP5
COMMAND
4
NOP5
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
x4: A13
x8: A12, A13
x16: A11, A12, A13
A10
t
IS
RA
RA
3
RA
t
IH
Bank
x
t
RCD
t
RAS
t
DQSS (NOM)
t
WR
t
RP
t
IS
t
IH
BA0, BA1
Bank
x
DQS
t
WPRES
t
WPRE
t
DQSL
t
DQSH
t
WPST
DQ
1
DM
t
DS
DI
b
t
DH
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DIn = data-out from column
n;
subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
Burst length = 4 in the case shown.
Enable auto precharge.
ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
See Figure 41, ”Data Input Timing,” on page 62 for detailed DQ timing.
-75
SYMBOL
MIN
MAX
UNITS
t
-75
SYMBOL
t
DSH
t
IH
t
IS
S
MIN
MAX
UNITS
t
CK
CH
t
CL
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DQSH
t
DQSL
t
DQSS
t
DSS
t
0.45
0.45
7.5
10
0.5
0.5
0.35
0.35
0.75
0.2
0.55
0.55
13
13
1.25
CK
t
CK
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
S
t
RAS
t
RCD
t
RP
t
t
WPRE
WPRES
t
WPST
t
WR
0.2
1
1
40
20
20
0.25
0
0.4
15
120,000
0.6
ns
ns
ns
ns
ns
t
CK
ns
t
CK
ns
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
70
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
