PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 46: Bank Read - Without Auto Precharge
CK#
CK
t
IS
t
IH
t
CK
t
CH
t
CL
T0
T1
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
CKE
t
IS
t
IH
ACT
t
IS
t
IH
Col
n
RA
NOP6
READ2
NOP6
PRE
7
NOP6
NOP6
ACT
COMMAND
5
NOP6
x4: A0-A9, A11, A12
x8: A0-A9, A11
x16: A0-A9
x4: A13
x8: A12, A13
x16: A11, A12, A13
A10
RA
RA
t
IS
RA
t
IS
t
IH
Bank
x
t
RCD
t
RAS7
t
RC
Bank
x
4
3
ONE BANK
RA
t
IH
ALL BANKS
RA
BA0, BA1
Bank
x
Bank
x
CL = 2
t
RP
DM
Case 1:
t
AC
(MIN)
and
t
DQSCK
(MIN)
t
RPRE
t
DQSCK
(MIN)
t
RPST
DQS
t
LZ
(MIN)
DQ
1
t
LZ
(MIN)
DO
n
t
AC
(MIN)
Case 2:
t
AC
(MAX)
and
t
DQSCK
(MAX)
t
RPRE
t
DQSCK
(MAX)
t
RPST
DQS
DQ
1
DO
n
t
AC
(MAX)
t
HZ
(MAX)
TRANSITIONING DATA
DON’T CARE
NOTE:
1. DOn = data-out from column
n;
subsequent elements are provided in the programmed order.
2.
3.
4.
5.
6.
7.
8.
Burst length = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T5.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
NOP commands are shown for ease of illustration; other commands may be valid at these times.
The PRECHARGE command can only be applied at T5 if
t
RAS minimum is met.
Refer to Figure 38 on page 60, Figure 39 on page 61, and Figure 40 on page 62 for detailed DQS and DQ timing.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
67
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
