512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 50:
Single WRITE – Without Auto Precharge
T0
CLK
tCKS
CKE
tCMS
COMMAND
tCMH
NOP
WRITE
NOP3
NOP3
PRECHARGE
NOP
ACTIVE
NOP
T1
tCK
tCKH
tCL
T2
tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS
DQM
tAS
ADDR
tAS
A10
tAS
BA0, BA1
tAH
ROW
tCMH
COLUMN
m
tAH
ROW
ALL BANKS
ROW
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
BANK
tAH
BANK
tDS
DQ
tRCD
tRAS
tRC
tDH
D
IN
m
tWR2
tRP
DON’T CARE
Notes:
1. For this example, BL = 1, and the WRITE burst is followed by a manual PRECHARGE.
2. 15ns is required between <D
IN
m>
and the PRECHARGE command, regardless of frequency.
3. PRECHARGE command not allowed or
t
RAS would be violated.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
67
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©2005 Micron Technology, Inc. All rights reserved.
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