512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Fig u re 11: READ Co m m a n d
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
COLUMN
ADDRESS
A0–A8
A9, A11, A12
EN AP
DIS AP
A101
BANK
ADDRESS
BA0, BA1
DON’T CARE
Notes: 1. EN AP = enable auto precharge
DIS AP = disable auto precharge
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z.
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL -1.
Figure 7 on page 16 shows CLs of two and three; data element n + 3 is either the last of a
burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule associated with a prefetch archi-
tecture. A READ command can be initiated on any clock cycle following a previous
READ command. Full-speed random read accesses can be performed to the same bank,
as shown in Figure 12 on page 25, or each subsequent READ may be performed to a
different bank.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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